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30 June 2019

Cadence Announced Complete, Silicon-Proven LPDDR5 IP SolutionComplete LPDDR5 IP Solution Includes Cadence PHY, Controller and Verification IP

June 30th, 2019 – Cadence Design Systems, Inc. announced early availability of the complete, silicon-proven Cadence® Denali® Gen2 IP for LPDDR5/4/4X in TSMC’s 7nm FinFET process technology. Offering up to 1.5X faster bandwidth than the fastest speed of LPDDR4 and LPDDR4X, the LPDDR5 standard enables high bandwidth with low power consumption, making it well suited for mobile computing, AI, IoT, cryptocurrency mining and automotive applications. The Cadence LPDDR5 IP solution consists of PHY, controller and Verification IP (VIP).

Cadence’s first offering in the LPDDR5 design IP product line supports the pre-release LPDDR5 standard and LPDDR4/4X devices to allow maximum flexibility for end products with a range of performance/cost targets and long production runs. Because it is a single-vendor solution, the new Cadence LPDDR5 IP reduces integration challenges between the PHY, controller and the rest of the SoC. Cadence deploys proven design techniques that reuse technology from Cadence’s silicon-proven DDR designs, lowering customers’ risk when implementing LPDDR5 IP. The Cadence LPDDR5/4/4X controller is based on the industry-leading Denali DDR controller, and customers benefit from a full set of popular features for memory interfaces, such as support for Arm® AMBA® AXI buses and reliability features like in-line error correcting codes.

“Cadence’s demonstration of LPDDR5 design IP that is silicon proven in TSMC 7nm FinFET process technology enables many future chips that will embrace the LPDDR5 technology,” said Suk Lee, senior director of Design Infrastructure Management Division at TSMC. “TSMC’s 7nm process technology continues to be the 7nm process of choice for advanced designs, including mobile and automotive applications that LPDDR5 primarily focuses on.”

“Our LPDDR5 design IP in TSMC’s 7nm process technology is fully operational with available LPDDR5 modules,” said Amjad Qureshi, corporate vice president, R&D, design IP at Cadence. “Following our first-to-market LPDDR4, LPDDR4X, DDR5 and GDDR6 announcements, Cadence continues to execute on our strategy of being first to silicon with the most advanced memory technology interface IP. Cadence’s collaboration with leading DRAM providers enhances compatibility between customers’ SoCs and memory devices. Customers also benefit from Cadence’s single-vendor solution and silicon-proven design techniques leveraged through multiple generations of DDR/LPDDR designs, which together reduce customers’ interoperability risk and accelerate chip integration time.”

Cadence LPDDR5 IP is available now for customer engagements. Design files are ready for select customers to begin integration work with confidence that the Cadence LPDDR5 IP will work as intended in its application.

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