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13 September 2019

Cadence Collaborates with TSMC to Accelerate 5nm FinFET Innovation, Enabling Next-Generation SoC Production Design

September 13th, 2019Cadence Design Systems, Inc. announced that it has collaborated with TSMC to enable customers’ production delivery of next-generation system-on-chip (SoC) designs for mobile, high-performance computing (HPC), 5G and artificial intelligence (AI) applications on TSMC’s 5nm FinFET process technology. As part of the collaboration, the Cadence® digital, signoff and custom/analog tools have been certified for Design Rule Manual (DRM) and SPICE v1.0, and Cadence IP has been enabled for the TSMC 5nm process. The corresponding process design kits (PDKs) featuring integrated tools, flows and methodologies are now available for traditional and cloud-based environments. Additionally, mutual customers have already completed several tapeouts using Cadence tools, flows and IP for full production development on the TSMC 5nm process technology.

To learn more about the Cadence full-flow digital and signoff advanced-node solutions, visit www.cadence.com/go/tsmc5nmds. For information about the Cadence custom/analog advanced-node solutions, visit www.cadence.com/go/tsmc5nmca. For information about Cadence IP, visit www.cadence.com/go/tsmc5nmip.

5nm Digital and Signoff Tool Certification

Cadence delivered a fully integrated digital implementation and signoff tool flow, which has been certified on TSMC’s industry-leading 5nm process that has the benefits of process simplification provided by extreme ultraviolet (EUV) lithography. The Cadence full-flow includes the Innovus™ Implementation System, Liberate™ Characterization Portfolio, Quantus™ Extraction Solution, Tempus™ Timing Signoff Solution, Voltus™ IC Power Integrity Solution and Pegasus™ Verification System.

The Cadence digital and signoff tools that have been optimized for TSMC’s 5nm process technology provide EUV support at key layers and associated new design rules, which enable mutual customers to reduce iterations and achieve performance, area, and power (PPA) improvements. Some of the newest enhancements for the 5nm process include predictive via-pillar-aware synthesis structuring with the Genus™ Synthesis Solution as well as a pin-access control routing method for cell electromigration (EM) handling in the Innovus Implementation System and Tempus ECO and also statistical EM budgeting analysis support in the Voltus™ IC Power Integrity Solution. The newly certified Pegasus Verification System supports 5nm rule decks for all TSMC physical verification flows including DRC, LVS and metal fill.

5nm Custom/Analog Tool Certification

The Cadence custom/analog tools certified on TSMC’s industry-leading 5nm process technology include the Spectre® Accelerated Parallel Simulator (APS), Spectre eXtensive Partitioning Simulator (XPS), Spectre RF Option, Spectre Circuit Simulator, Voltus-Fi Custom Power Integrity Solution, Pegasus Verification System as well as the Virtuoso® custom IC design platform, which includes the Virtuoso Layout Suite EXL, Virtuoso Schematic Editor and Virtuoso ADE Product Suite.

The Virtuoso R&D team has an ongoing and rich collaboration with the Cadence IP Group, developing 5nm mixed-signal IP using a state-of-the-art custom design methodology built on the latest Virtuoso design platform. By continually enhancing the design methodologies and capabilities included with the Virtuoso Advanced-Node and Methodology Platform for TSMC’s advanced-node processes, including the 5nm process, customers can achieve better custom physical design throughput versus traditional non-structured design methodologies.

The new Virtuoso Advanced-Node and Methodology Platform (ICADVM 18.1) consists of features and functionality required for creating 5nm designs, which include an accelerated, row-based custom placement and routing methodology that enables users to improve productivity and better manage complex design rules. Cadence introduced several new features that support the 5nm process including stacked gate support, universal poly grid snapping, area-based rule support, asymmetric coloring and voltage-dependent rule support, analog cell support and support for various new devices and design constraints that are part of TSMC’s 5nm technology offering.

5nm IP Enablement

Cadence is developing a differentiated advanced-node IP portfolio to support TSMC’s 5nm process, which includes a high-performance memory subsystem, very high-speed SerDes and high-performance analog to meet the demands of HPC, machine learning (ML) and 5G base stations. With the release of TSMC’s 5nm design infrastructure, Cadence and TSMC are actively engaged with customers and enabling next-generation SoC development by addressing the latest IP requirements for evolving application areas.

“TSMC’s 5nm technology offers our customers the industry’s most advanced technology to address the growing demand for computing power driven by AI and 5G,” said Suk Lee, TSMC senior director, Design Infrastructure Management Division. “By collaborating closely with Cadence, we’re enabling customers to effectively differentiate themselves and deliver designs to market faster using our latest technologies.”

“We’re continuing to broaden our collaboration with TSMC to facilitate 5nm FinFET adoption, giving customers access to the latest tools and IP for advanced process design creation,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “Our R&D team has focused heavily on developing new features and performance improvements so that our digital and signoff and custom/analog tools and IP can be used with complete confidence, enabling customers to achieve first-pass silicon success and deliver end products within aggressive time-to-market schedules.”

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