December 3rd, 2019 — Mobiveil, Inc. a fast-growing supplier of silicon intellectual property (SIP), platforms and IP-enabled design services, announced availability of its PCI Express? 5.0 controller IP with end-to-end data path protection. While supporting raw speed is essential, Mobiveil?s PCIe? 5.0 architecture IP ensures high degree of configurability, reliability and serviceability, crucial for supporting critical applications in Networking, Storage, Server, AI, Telecom, Consumer and IOT. This PCI Express 5.0 technology IP complements Mobiveil?s rich portfolio of high-speed controller IPs that includes RapidIO, NVM Express, DDR Controller, Flash controllers and LDPC flash reliability controller.
?We are pleased to offer the latest generation of PCI Express 5.0 controller IP to our customers,? said Ravi Thummarukudy, CEO of Mobiveil Inc. ?Previous versions of our GPEX PCI Express IP enjoyed wide adoptions with major semiconductor and system companies and now we hope to build on our experience and offer PCIe 5.0 architecture IP for many advanced applications. Our IP offerings have a proven track record and have been seamlessly integrated with all major PHY and VIP vendors. The PCI Express interface has seen a dramatic increase in demand, thanks to data centers installing rapidly increasing numbers of servers and solid-state drives (SSDs). The availability of the PCI Express 5.0 specification will also provide processors targeting high performance applications much needed throughput.?
PCI Express 5.0 Specification Protocol Interface
Mobiveil?s new controller IP achieves the full PCIe 5.0 specification 32Gbs bit rate per lane and is backward compatible with PCIe versions 4.0, 3.1, 2.0 and 1.1. Mobiveil offers all flavors of PCI Express including Root Complex, End Point, Dual mode and Switch configurations. Mobiveil PCI Express controller also provides AXI interface for easy integration into SoC designs. In addition, the controller interfaces a wide variety of PHYs available from third parties. The controller accommodates PIPE (PHY Interface for the PCI Express) 8 bit, 16-bit, 32-bit and 64-bit in x1, x2, x4, x8 and x16 implementations. The PCIe 5.0 controller supports SR-IOV (Single Root I/O Virtualization), ARI (Alternate Routing Interpretation) and Address Translation Services.
Mobiveil?s PCIe 5.0 Controller architecture optimizes link utilization, latency, reliability, power consumption, and silicon footprint. Controller handles PCI Express ordering rules and implements Multiple VCs and associated flow control logic in both directions. The packet-oriented user logic interface also supports PIPE 5.0-compliant PHYs, and flexible lane ordering and support for lane reversal.
?We are excited to collaborate with Mobiveil to bring total, best in class robust pre-validated IP solutions to our customers and streamline the design and verification process and foster the rapid adoption of the next generation PCIe 5.0 standard,? said Chris Browy, vice president of sales/marketing at Avery. ?Mobiveil and Avery are long-term partners and are both respected leaders in SIP and VIP.? Avery provides a complete System Verilog/UVM verification solution including models, protocol checking, and compliance test suites for Root Complex, SR-IOV Endpoint, and Switch and Repeater verification.
Tags: Mobiveil, PCI Express 5.0