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29 May 2019

Wave Computing Adds MIPS32 microAptiv Cores to MIPS Open ProgramNew Release of MIPS Open™ Components Includes Verilog RTL Code for MIPS32 microAptiv Cores Helping Developers Save Months-to-Years of Time

May 29th, 2019Wave Computing, Inc., the Silicon Valley company accelerating artificial intelligence (AI) from the datacenter to the edge, announced it will include the MIPS32® microAptiv™ cores in the newest release of MIPS Open program components. One of the smallest and low power CPUs in the MIPS product line, the MIPS32 microAptiv core is a highly-efficient, compact, real-time solution for microcontrollers (MCU) and entry-level embedded market applications such as automotive, Internet of Things (IoT) and home networking appliances. The Verilog register transfer level (RTL) code for the MIPS32 microAptiv cores and other MIPS Open program components are available for immediate download.

“When the MIPS32 microAptiv core was introduced, it delivered much higher clock speeds than other MCU cores as well as better code density,” said Linley Gwennap, principal analyst of The Linley Group. “Now that Wave Computing is offering microAptiv in the MIPS Open components, SoC designers are free to integrate this reliable and powerful CPU without any license fees or royalties. This announcement marks a significant advance for the MIPS Open initiative.”

The MIPS32 microAptiv core is designed for low power, high-performance and cost sensitive applications such as vehicle dashboard systems, building environmental controls, and consumer appliance control modules. Its efficient Digital Signal Processing (DSP) capabilities make it ideal for use in multimedia or digital applications that are often reprogrammed for use in different applications. The MIPS32 microAptiv core also includes Code Compression capabilities that help run the code on a reduced amount of memory—a key feature when designing for small surfaces where each millimeter counts.

The new set of MIPS Open program components will include two different versions of the microAptiv Verilog RTL code:

– microAptiv MCU core – designed with application-specific features and real-time performance for microcontroller SoC development;

– microAptiv MPU core – includes a cache controller and MMU facilitating embedded system designs executing operating systems such as Linux.

In addition to the Verilog RTL code, the package also includes documentation, configuration tools and a verification suite.

“The Wave Computing team is delighted to make its MIPS32 microAptiv cores available for MIPS Open participants. The microAptiv cores have already been embedded into millions of commercial designs worldwide that we use every day,” said Krishna Raghavan, president of Wave Computing’s MIPS IP Licensing business. “By making these cores available to SoC designers via the MIPS Open program, our hope is to accelerate the next generation of highly-efficient, intelligent, IoT, consumer and automotive applications.”

For more information on the newest batch of MIPS Open components or to register as a new member of the MIPS Open ecosystem, visit www.mipsopen.com.

The original of this article

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