May 23rd, 2018 — The world-leading research and innovation hub in nanoelectronics and digital technologies, imec, and Cadence Design Systems, Inc. announced that its extensive, long-standing collaboration has resulted in the industry?s first 3nm test chip tapeout. The tapeout project, geared toward advancing 3nm chip design, was completed using extreme ultraviolet (EUV) and 193 immersion (193i) lithography-oriented design rules and the Cadence? Innovus? Implementation System and Genus? Synthesis Solution. Imec utilized a common industry 64-bit CPU for the test chip with a custom 3nm standard cell library and a TRIM metal flow, where the routing pitch was reduced to 21nm. Together, Cadence and imec have enabled the 3nm implementation flow to be fully validated in preparation for next-generation design innovation.
The Cadence Innovus Implementation System is a massively parallel physical implementation system that enables engineers to deliver high-quality designs with optimal power, performance and area (PPA) targets while accelerating time to market. The Cadence Genus Synthesis Solution is a next-generation, high-capacity RTL synthesis and physical synthesis engine that addresses the latest FinFET process node requirements, improving RTL designer productivity by up to 10X.
For the project, EUV and 193i lithography rules were tested to provide the required resolution, while providing PPA comparison under two different patterning assumptions.
?As process dimensions reduce to the 3nm node, interconnect variation becomes much more significant,? said An Steegen, executive vice president for semiconductor technology and systems at imec. ?Our work on the test chip has enabled interconnect variation to be measured and improved and the 3nm manufacturing process to be validated. Also, the Cadence digital solutions offered everything needed for this 3nm implementation. Due to Cadence?s well-integrated flow, the solutions were easy to use, which helped our engineering team stay productive when developing the 3nm rule set.?
?Imec?s state-of-the-art infrastructure enables pre-production innovations ahead of industry demands, making them a critical partner for us in the EDA industry,? said Dr. Chin-Chi Teng, corporate vice president and general manager in the Digital & Signoff Group at Cadence. ?Expanding upon the work we did with imec in 2015 on the industry?s first 5nm tapeout, we are achieving new milestones together with this new 3nm tapeout, which can transform the future of mobile designs at advanced nodes.?
Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company?s System Design Enablement strategy helps customers develop differentiated products?from chips to boards to systems?in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine’s 100 Best Companies to Work For.
Imec is the world-leading research and innovation hub in nanoelectronics and digital technologies. The combination of our widely acclaimed leadership in microchip technology and profound software and ICT expertise is what makes us unique. By leveraging our world-class infrastructure and local and global ecosystem of partners across a multitude of industries, we create groundbreaking innovation in application domains such as healthcare, smart cities and mobility, logistics and manufacturing, energy and education.
As a trusted partner for companies, start-ups and universities we bring together close to 3,500 brilliant minds from over 70 nationalities. Imec is headquartered in Leuven, Belgium and has distributed R&D groups at a number of Flemish universities, in the Netherlands, Taiwan, USA, China, and offices in India and Japan. In 2016, imec’s revenue (P&L) totaled 496 million euro.