July 30th, 2019 — With TSMC providing a wider array of technologies than ever, we are expanding our design enablement solutions to match. The very latest offerings from TSMC?s design service team support a broad spectrum of customer designs, ranging from advanced technologies at the leading edge of Moore?s Law, to low-power technologies for wearables and IoT, to automotive and advanced 3D-IC packaging. To address the critical design challenges associated with 7nm plus, 5nm and 3D-IC for SoC applications, we announced the New reference flows featuring FinFET-specific design solutions and methodologies for performance, power, and area optimization. TSMC has also expanded its library and silicon IP portfolio to contain more than 20,000 IP titles, a 25% increase over the past year, and we provided more than 9,000 technology files and more than 300 PDKs via TSMC-Online. There are more than 100,000 customer downloads of these files each year. The latest addition includes offering a Virtual Design Environment on secure cloud platforms with leading EDA partners.
Below are some of the highlights of TSMC?s latest design enablement offerings:
? 5nm technology is ready for design start and on schedule for volume production in first half of 2020. Design flow has been validated on test vehicles and Version 0.9 certification for EDA tool providers is now complete. Functionality and circuit architecture of foundation IP is validated on silicon and design kits are ready for design start, with a broad variety of IP from OIP ecosystem partners in development.
? 7nm FinFET Plus process technology, the first commercially available EUV-enabled foundry process technology, entered risk production in August 2018, with our design enablement minimizes the effort needed to port 7nm designs, and has been deployed in leading customers? new tape-outs. Foundation IPs are silicon validated and interface IPs are ready for design today.
? 22nm Ultra-Low Power (22ULP) and 22nm Ultra-Low Leakage (22ULL) are supported by the industry?s most complete 22nm technology platform with the same design rules as 28nm High Performance Compact Plus technology. Version 1.0 EDA certification is complete and IP portfolio is ready for design.
? 16nm FinFET Compact Technology automotive design enablement platform is in production, and 7nm automotive design enablement platform will be ready in this quarter 1Q19.
? 3D-IC technology and design enablement platforms cover a wide range of applications; Wafer-on-Wafer (WoW), InFO on substrate (InFO_oS), InFO with memory on substrate (InFO_MS), and CoWoS are all in production. The innovative 3D multi-chip stacking provided by System on Integrated Chips (SoIC) will be available this quarter 1Q19.
? The initial availability of Open Innovation Platform? Virtual Design Environment (OIP VDE), which enables semiconductor customers to securely design in the cloud, leveraging TSMC OIP design infrastructures within the flexibility of cloud infrastructures. OIP VDE is the result of TSMC collaboration with TSMC OIP design ecosystem partners and leading cloud providers to deliver a complete systems-on-chip (SoCs) design environment in the cloud.